1. Field of the Invention
The present invention relates to a semiconductor device having a MOS (Metal Oxide Semiconductor) transistor and a method for manufacturing the same.
2. Description of Related Art
A DRAM (Dynamic Random Access Memory) is a device having a plurality of memory cells which combine a MOS transistor and a storage element serving as a capacitor. In a general memory cell, a gate electrode of the MOS transistor is formed on a silicon (Si) substrate. A line connecting the gate electrodes of the adjacent memory cells is called a word line.
Japanese Patent Laid-Open No. 2000-164833 has proposed a memory cell having a structure in which a word line is provided inside the substrate unlike a general memory cell structure. The disclosed memory cell uses a trench gate MOS transistor in which a word line is provided in a trench of the substrate.
In a general memory cell structure, a word line is formed on the Si substrate via a gate oxide film, and a wiring layer used for a bit line is formed on an upper layer above the word line. In order to electrically connect an impurity diffusion layer serving as a source electrode and a drain electrode of the MOS transistor provided on the Si substrate surface and a wiring layer serving as the bit line, a plurality of contact plugs need to be provided therebetween. Moreover, the wiring layer needs to be provided at a position not shorted to the storage element formed on an upper layer above the MOS transistor. For this reason, a contact forming method such as a self align contact is used to form a contact having electric insulation. Although there is increased demand for microfabrication, it is difficult to create such a contact.
Furthermore, the memory cell structure proposed in Japanese Patent Laid-Open No. 2000-164833 is not sufficient to meet the request for further microfabrication.